ops-compute-01 · MB-1 · round 1

Compute & Silicon

The compute center is where the whole city closes its loop. Since this round the big screen runs the MB-1 algorithm itself, bit-exact — same LFSR, same clamped inverse-CDF walk, same 4096-word table — and self-tests against the Python golden on boot. MB-1 was taken from Verilog to a sky130 GDS. No silicon exists and the evaluation board was designed but never ordered; the page says so. And the room around them is now a room that can be accounted for on Mars: six ledgers size its racks, its cooling loop, its radiator field, its feeder, its data link, and say what they cannot close.

MB-1 die (design)
1.79mm² · 4 SRAM macros = 63.5%
Screen self-test
PASS220 chars vs Python golden
Radiator field
162m² · 3 panels · 70° north
Science data in
15.4GB/sol · Earth link takes 10.7
01

What it is

A datacenter hall whose hero screen runs an AI — the AI's silicon body is designed one rack over — and every wall, panel and pipe now has a number behind it.

The big screen types Mars text character by character. In v0 it ran a bigram of the same class as the chip's, counted live in the browser with Math.random(). That sentence on the old card — "the same algorithm as the wall display" — did not survive this round's audit, so the screen was changed rather than the card: it now imports the chip's own CDF table (mb1-cdf-data.js, generated from build/mb1_cdf.mem), runs the chip's arithmetic, and prints MB-1 bit-exact vs python golden: PASS in its boot log. If that line ever reads FAIL it is red. The table is trained on the city's own seven Mars sentences, which are now also MB-1's training corpus.

MB-1 is that algorithm as a digital ASIC design: RTL, two simulators in lock-step, Vivado synthesis, an Arty bitstream, a Yosys sky130 netlist and an OpenROAD place-and-route to a 1.79 mm² GDS. The evaluation board on the rack-2 tray is drawn from the board's real layout (467 routed segments) — a design with Gerber files, 57 clearance violations still open, never ordered. The package in the socket is a prop. The earlier page header called the board "fabbed"; that word is retired.

The rest of the building is what changed most. The fin wall of v0 was a drawing; the radiator field is now sized by a heat account with two independent view-factor methods and an ISS known-answer gate. The eight racks are booked by the grid dossier at 40/55 kW — a capacity read off the drawing, which the load account could not match to any card-priced load. The radiation account is declared not closable until sci-rad-01 hands over the surface spectrum. Every one of those statements has a script, a JSON product and a pre-registered expectation behind it.

The refined compute center by day: hall with glass front, three tilted radiator panels to the west
ROUND 1 BY DAY — HALL, AIRLOCK, CDU LOOP THROUGH THE WEST WALL, THREE 12 × 4.5 m PANELS AT 70° FACING NORTH
The compute center at night, screen light washing the hall
ROUND 1 AT NIGHT — SCREEN WASH, RACK LEDS, WARNING LAMP ON THE RADIATOR MAST
MB-1 evaluation board as a blade in the compute-center rack
MB-1 EVAL BOARD ON THE RACK-2 TRAY — REAL LAYOUT COPPER; A DESIGN, NOT A BUILT BOARD; THE PACKAGE IS A PROP
02

How it works

Training stays off-chip; on-chip inference collapses to “one 16-bit random number × a run of compares.” Around the chip, six accounts.

Count the bigram transitions offline, turn each row into a cumulative distribution, normalize to 16-bit full scale, write it into on-chip SRAM over SPI. Sampling is inverse-CDF: draw a 16-bit random number, clamp it to [1, 0xFFFF], walk the row until CDF[i] ≥ r. No multiply, no divide, no float — comparators, a counter and a 32-bit LFSR. The 64-kbit table is four compiled OpenRAM macros, never flip-flops, and on the die they take 63.5% of the area.

The chip was carried through RTL → FPGA → sky130 GDS → PCB design. Three implementations agree bit for bit by log (Python golden, iverilog, xsim); synthesis and place-and-route are report-level products. Post-silicon evidence does not exist because there is no silicon.

RTL · 7 modules, self-checking TB FPGA · Arty A7-35T bitstream (rebuilt on the Mars table) sky130 · Yosys → OpenROAD GDS PCB · Gerber / BOM / CPL, unordered
1 · Load

What the city computes, by the units in it today. 35 rows, each with a card commit; 8 declared gaps. The largest compute item is the radio array's 605 GFLOP/s correlator, on site. What reaches this room is data: 15.4 GB/sol, 10.3 TB per Mars year. No card places a compute load here — the grid's 40/55 kW is a drawn capacity, and the card now says so.

2 · Power

IT + cooling + storage. No chiller: pumps 1.9 kW at 55 kW IT, conversion loss 1.9 kW at 96.6%, PUE 1.08. The G-C north trunk (1200 kW) carries 70 kW of served peaks — no village-type spur defect. Island share: 0 kW mandatory; the grid's 4.8 kW "SCADA UPS inside" is not endorsed, because the SCADA is in the grid's own control room.

3 · Heat

Stefan-Boltzmann to a 210 K sky and a 260 K ground, dust at α 0.68. The v0 fin wall rejects 49–69 kW at 320 K (more than pre-registered), but any sky-facing surface loses half its rejection to the noon sun once dusted. The winning family is near-vertical, north/south faces: 570 W per m² of panel at the worst noon, 889 at night. 59.4 kW needs 104 m²; 162 m² built.

4 · Radiation

Not closable, now confirmed by the holder. A surface room under 20.7 g/cm² of CO₂ and 234 mSv/yr, wall not folded in. sci-rad-01 holds no measured spectrum; its charged-particle flux is 3 /cm²/s, a background-knowledge value. The earlier 8.9 /cm²/s on this page was a pixel-hit rate per area, retired 2026-09-13. SEU is a sweep over the per-bit cross-section: in quiet time the SEC-DED verdict still flips inside the sweep; during a hard S5 event uncorrectables rise by 10⁷, so the policy needs a second knob, an accelerated scrub on the SEP alert. SEL stays unknown: it "depends on a recoil population this station cannot count with a single layer" (sci-rad-01).

5 · Audit

23 claims of the old card and this page, each against a product. 11 supported, 5 with a stated limit, 3 partly, 2 designed-not-built, 1 with no product at all, 1 contradicted by its own report (267 LUT, retired → 212). Logs were re-run and filed so that "two simulators tick-identical" is a file, not a sentence.

6 · Data link

In 15.4 GB/sol, out 10.7. The planet's Earth link averages 0.965 Mbps; the room is where science data lands, is reduced and is kept. The teal cable from the blade to the screen stands for a 115.2 kbit/s UART carrying ~130 bit/s; MB-1 at full speed would outrun it 200×.

sky130 GDS layout of MB-1 showing four SRAM macros
MB-1 sky130 DIE 1660×1080 µm — FOUR SRAM MACROS (2×2) = 63.5% OF AREA, LOGIC AT CENTER. A GDS, NOT A PHOTOGRAPH
MB-1 evaluation board PCB layout
MB1-DEMO revA — 2-LAYER BOARD DESIGN, 467 ROUTED SEGMENTS; 57 CLEARANCE VIOLATIONS OPEN, NOT ORDERED
Close-up of the MCU LQFP fanout on the PCB
LQFP-48 FANOUT ZOOM — THREE-STEP STAGGERED ESCAPE VIAS, THE CLEARANCE-FIX ZONE
03

The ledger

Every headline number, which script or report produced it, and whether it is a design figure or a measurement.

ClaimValueStateProduced by
Screen sampler bit-exact vs Python goldenPASS · 220 chars @ seed 0x12345678measured (node + browser)viewer/units/ops-compute-01.js + mb1-cdf-data.js; ledger/out/05_mb1_audit.json
Three implementations bit-exactPython ↔ iverilog ↔ xsim · 0 mismatchlogledger/logs/iverilog_tb_mb1.log, xsim_tb_mb1.log
Two simulators tick-identical$finish 1,131,905 ns bothlogsame logs (Mars-corpus table; the old table's time retired with it)
FPGA OOC synth, latches0 · 212 LUT / 292 FFreportsyn/reports/utilization.rpt (212 formerly printed as 267 — retired)
FPGA Fmax173 MHz (WNS −0.781 ns @200 MHz)reportsyn/reports/timing_summary.rpt
Arty bitstream, timingMET · WNS +3.289 ns @100 MHzreport (never loaded on a board)ledger/logs/vivado_impl_arty.log, fpga/arty_build/
sky130 logic area33,123 µm² · 2245 cells incl. 4 macrosreportasic/reports/sky130_stat.txt
SRAM macro equivalence11,069 reads · 0 mismatchlogledger/logs/iverilog_tb_cdf_sram_equiv.log
Full die, routing DRC1.79 mm² · DRC report emptyreport (empty file: limit stated)asic/pnr/mb1_pnr.tcl, asic/pnr/out/route_drc.rpt
Timing at 100 MHzhold +0.14 MET · setup −0.02 VIOLATED → clean ≤ 99.6 MHzreportasic/pnr/out/final_timing.rpt
Core power29.6 mW @100 MHzestimate (no silicon)asic/pnr/out/final_power.rpt
Final GDS27,550,944 Bfileasic/pnr/merge_gds.ps1 (klayout)
PCB net truth-table129 pins · 0 mismatchfile, no run logpcb_skill/scripts/verify_sch.py + pcb/mb1_truth.json
Board routed0 routing fails · 57 clearance DRC openlogpcb/route13.log (pcb/mb1_route_board.py)
Science data ingest15.4 GB/sol · 10.3 TB / Mars yearfrom cardsledger/01_load.py → out/01_load.json
Digital twin render load2.97 M tris · 7022 calls · 55.7 ms/framemeasuredledger/inputs/twin_measurement_2026-09-06.json
IT load hosted hereNOT CLOSABLE (grid books 40/55 kW capacity)declared gapledger/out/01_load.json totals.hosted_here_note
PUE1.079 peak · pumps 3.5% of ITaccountledger/02_power.py → out/02_power.json
Feeder served peaks70 kW of 1200 kW (5.8%)from grid jsonledger/02_power.py; mars-grid out/03_transmission.json
v0 fin wall at 320 K69 night / 57 day / 49 day+sun kWaccount (retired geometry)ledger/03_thermal.py → out/03_thermal.json drawn_wall_320K
Panel design flux (dusted, 320 K)570 W/m² worst noon · 889 nightaccountledger/out/03_thermal.json two_sided_panel_table
ISS known-answer gatemodel 259 vs ISS 147 W/m² planform (×1.76)gateledger/03_thermal.py G3.1
Radiator field3 × 12×4.5 m · 162 m² · 92–144 kWdesign from accountledger/out/03_thermal.json geometry_for_asset
Surface charged-particle flux3 /cm²/s (8.93 retired: a pixel-hit rate per area)holder's background-knowledge valueledger/04_radiation.py r1.1; sci-rad-01 replies e2ed278 / efa91c6
SEU / SEL rateNOT CLOSABLE (holder has no spectrum)declared gapdev/REPLY_sci-rad-01_to_ops-compute-01_spectrum.md + _products.md
LET unit conversion in Si1 keV/µm = 0.00429 MeV·cm²/mg (MIP check: 116.3 keV in 300 µm)known-answer gateledger/04_radiation.py G4.5
φ(>LET) table from the ΔE–E telescoperegistered, used in no ratedesign simulation, no data (sci-rad-05)ledger/out/04_radiation.json sci_rad_05_table_2b
Uncorrectables in a hard S5 SEP×9.6×10⁶ (flux ×3103, squared)account on an extrapolated fluxledger/out/04_radiation.json sep_S5_sweep_64GB
Earth link mean0.965 Mbps = 10.7 GB/solfrom relay cardledger/06_datalink.py → out/06_datalink.json
Blade-to-screen cableUART 115.2 kbit/s · ~133 bit/s usedaccountledger/out/06_datalink.json cable
Roster and quota board5,136 tris · reads roster-data.js at buildhosted part (ops-roster-01), data not transcribedviewer/units/roster-board.js + roster-data.js
In-city smoke testscale 1 · 57 assets · self-test PASS · 1 console 404 (sci-rad-05 card, not this unit)measureddev/DELIVERY_ops-compute-01_r1_1.md
04

What broke

The honest part. Two RTL bugs and thirteen routing rounds from the first build — and, this round, what the accounts overturned in the page itself.

The page said "fabbed"; the card said "engineering sample" — both withdrawn, neither exists.

The truth audit found three sentences that read as built where only design files exist, all three now withdrawn: a "fabbed eval board", a "gold-lidded ceramic engineering sample in the DIP-24 socket", and "MB1-DEMO revA" as if it were a board — retired on the card with the old wording kept in quotes and the date. The dossier ends at GDS and Gerber.

267 LUTs, retired: the report says 212

The stored synthesis report says 212 (200 logic + 12 distributed RAM); 267 had been carried from an earlier run into the README, the card and this page. The report wins. Same audit: "bit-exact across four tools" was three simulators plus a synthesis report; and the page printed hold slack (+0.14 ns MET) while omitting the setup violation in the same file (−0.02 ns at 100 MHz).

"Same algorithm as the wall display" was not true until this round

The v0 screen program was a floating-point bigram counted in the browser with Math.random(). The chip's table and arithmetic now run on the screen and self-test on boot; the corpus was switched to the city's own text and every build product, both simulator logs, the twin page and the Arty bitstream were regenerated on the new table.

Three of four thermal expectations missed

Pre-registered before computing: the fin wall would reject 20–45 kW (it rejects 69 at night); day would fall 30–60% below night (17%); a sky-facing tilted panel would net 250–400 W/m² (466 for the whole panel, and the best family is near-vertical). Wrong on the inter-fin escape (31%, not ~10%), wrong on how much a dusted surface absorbs at noon, wrong on how cold the ground is. Expectations were left as written; the conclusions changed.

A pixel-hit rate read as a particle flux, and a gate that could not go red

The radiation account divided the rad station's 62 hits per second by its chip area and printed a charged-particle flux of 8.9 /cm²/s, now retired. The holder answered that 62 counts pixels, not particles (about three pixels per track, since revised by the holder to 9.5), and that its particle flux is 3 /cm²/s. The 8.93 figure is retired. The gate that "checked" it multiplied the same two numbers back together, an identity; it is replaced by a gate on the holder's own decomposition, which closes at 197.8 against 198 hits per second.

A unit column 100× off, copied once before it was caught

The particle telescope sent a φ(>LET) table whose MeV·cm²/mg column used 1/2.33 where 1/233 is right; the rad station's reply carried the same slip, and this dossier had copied one such figure into a ledger file a week earlier. It is retired there. A minimum-ionising particle settles it: 116 keV in 300 µm of silicon with the right constant, 1.16 keV with the wrong one. Which LET range sets latch-up for the devices is now registered as open.

A view-factor model 20% high, and a gate that asserted a wish

The first analytic wall model used a cavity-aperture emissivity outside its small-aperture assumption and disagreed with the ray-cast by 20%; the cross-check gate went red, the model was replaced by parallel-plate view factors with a reflection series, and the two now agree within 1.3%. In the radiation account the first gate said "the ECC verdict does not flip across the sweep" — a wish, not a mechanism — and went red because the verdict does flip. It was replaced by a gate on the formula's scaling; the flip is reported.

The grid closed the room twice against the same drawing

The grid dossier's "8 racks × 5 kW = 40 kW, agrees within 9%" with the grid's second-route figure of 43.6 kW for the v0 wall is two readings of the v0 drawing agreeing with each other. The wall figure lies inside this account's 49–69 kW for that wall; the load side matches no card. Reported back as "installed capacity, demand unpriced" rather than corrected in their file.

The new footprint crossed a heat pipe

Widening the unit from 26 to 42 m put its west edge over the pipe-heat-2 corridor; the layout audit said ROAD CLASH. The site moved 8 m east; audit clean, placements registry updated.

From the first build, still true

Sampling off-by-one (r = 0 could pick a zero-probability symbol; clamped), a zero-width VALID pulse when READY was held high (registered valid), the SRAM that synthesized to 66,048 flip-flops until it was read as a macro, six place-and-route rounds, and the USB-C connector that deadlocked the router until it became a Micro-USB.

05

Try it

Walk into the compute center and read the boot log.

MB-1 board glowing in the compute center at night
NIGHT SHIFT — THE BLADE ON ITS TRAY, HEARTBEAT LED PULSING; THE BOARD IS A DESIGN, THE LED IS THE MODEL'S